Publications

🟦: Interconnection networks, 🟪: Custom computing with FPGAs, 🟩: Parallel computing with GPUs, 🟥: Solid-State Circuits

International Journal Papers
  1. 🟪 accepted
  2. 🟩 [JPDC] Ryota Yasudo, Koji Nakano, Yasuaki Ito, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano, "GPU-accelerated Scalable Solver with Bit Permutated Cyclic-Min Algorithm for Quadratic Unconstrained Binary Optimization", Journal of Parallel and Distributed Computing, vol. 167, pp. 109-122, 2022.
  3. 🟩 [CCPE] Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano, "Simple Iterative Trial Search for the Maximum Independent Set Problem Optimized for the GPUs", Concurrency and Computation: Practice and Experience, 2021.
  4. 🟪 [CCPE] Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano, "High-throughput FPGA Implementation for Quadratic Unconstrained Binary Optimization", Concurrency and Computation: Practice and Experience, 2021.
  5. 🟪 [TRETS] Ryota Yasudo, Jose Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo, "Analytical Performance Estimation for Large-scale Reconfigurable Dataflow Platforms", ACM Transactions on Reconfigurable Technology and Systems, Vol. 14, No. 3, Article 12, pp. 1-21, 2021.
  6. 🟦 [CCPE] Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "Designing Low-Diameter Interconnection Networks with Multi-ported Host-Switch Graphs", Concurrency and Computation: Practice and Experience, December 2020.
    https://doi.org/10.1002/cpe.6115
  7. 🟦 Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks", IEICE Transactions on Information and Systems, Vol. E103-D, No.12, December 2020.
  8. Carlos C. Cortes Torres, Ryota Yasudo, and Hideharu Amano, "Body Bias Optimization for Real-Time Systems", J. Low Power Electron. Appl., February 2020.
  9. 🟦 Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, "A Generalized Theory based on the Turn Model for Deadlock-Free Irregular Networks", IEICE Transactions on Information and Systems, Vol. E103-D, No. 1, pp. 101-110, January 2020.
  10. 🟪 [CCPE] Takuma Wada, Naoki Matsumura, Ryota Yasudo, Koji Nakano, and Yasuaki Ito, "Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA", Concurrency and Computation: Practice and Experience, August 2019.
    https://doi.org/10.1002/cpe.5475
  11. 🟦 [IEEE TPDS] Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, and Hideharu Amano, "Designing High-Performance Interconnection Networks with Host-Switch Graphs", IEEE Transactions on Parallel and Distributed Systems, vol. 30, no. 2, pp. 315-330, February 2019. (Date of Publication on IEEE Xplore: 07 August 2018)
    [IEEE Xplore] [Paper]
  12. 🟦 [IEEE TC] Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tadao Nakamura, "Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers", IEEE Transactions on Computers., vol. 66, no. 4, pp. 702-716, April 2017. (Date of Publication on IEEE Xplore: 07 September 2016)
International Conference/Symposium Proceedings
  1. 🟪 [FPT'23] Ryota Miyagi, Ryota Yasudo, Kentaro Sano, and Hideki Takase, "Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA clusters", in Proc. of International Conference on Field Programmable Technology (FPT) (Ph.D. Forum), Yokohama, Japan, December 2023. (to appear)
  2. 🟦 [CANDAR'23] Masashi Oda, Kai Keida, and Ryota Yasudo, "Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints", in Proc. of International Symposium on Computing and Networking, Matsue, Japan, November 2023. (to appear)
  3. 🟩 [PDP'23] Ryota Yasudo, "Bandit-based Variable Fixing for Binary Optimization on GPU Parallel Computing", in Proc. of Euromicro International Conference on Parallel, Distributed, and Networ-Based Processing (PDP), Naples, Italy, March 2023.
  4. 🟥 [ISSCC'23] Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, and Masato Motomura, "Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension", in Proc. of International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United States, February 2023.
  5. 🟪 [FPT'22] Ryota Miyagi, Ryota Yasudo, Kentaro Sano, and Hideki Takase, "Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning", in Proc. of International Conference on Field Programmable Technology (FPT), Hong Kong, China, December 2022.
  6. 🟪 [FPL'22] Kohei Ito, Ryota Yasudo, and Hideharu Amano, "Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches", in Proc. of 32nd International Conference on Field Programmable Logic and Applications (FPL), Belfast, United Kingdom, August 2022. [Video]
  7. 🟩 [APDCM'22] Ryota Yasudo, Koji Nakano, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane, and Kenichiro Hamano, "Graph-theoretic Formulation of QUBO for Scalable Local Search on GPUs", in Proc. of 24nd Workshop on Advances in Parallel and Distributed Computational Models (APDCM) in conjunction with International Parallel and Distributed Processing Symposium (IPDPS), Online, May 2022.
  8. 🟩 [CANDAR'21] Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane, and Kenichiro Hamano, "Solving the sparse QUBO on multiple GPUs for Simulating a Quantum Annealer", Proc. of International Symposium on Computing and Networking, Online, November 2021.
  9. 🟪 [CANDAR'20] Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, and Kenichiro Hamano, "Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA", Proc. of International Symposium on Computing and Networking, Online, November 2020. (Best Paper Award)
  10. 🟩 [CANDAR'20] Tomohiro Imanaga, Koji Nakano, Masaki Tao, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, and Kenichiro Hamano, "Efficient GPU Implementation for Solving the Maximum Independent Set Problem", Proc. of International Symposium on Computing and Networking, Online, November 2020.
  11. 🟩 [ICPP'20] Ryota Yasudo, Koji Nakano, Yasuaki Ito, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, and Yoko Inaba, "Adaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs", Proc. of the International Conference on Parallel Processing (ICPP), Online, August 2020. (Acceptance rate: 78/269 = 29.0%)
    [Video] [Paper]
  12. 🟩 [APDCM'20] Masaki Tao, Koji Nakano, Yasuaki Ito, Ryota Yasudo, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, and Yoko Inaba, "A Work-Time Optimal Parallel Exhaustive Search Algorithm for the QUBO and the Ising model, with GPU implementation", in Proc. of 22nd Workshop on Advances in Parallel and Distributed Computational Models (APDCM) in conjunction with 33rd IEEE International Parallel and Distributed Processing Symposium (IPDPS), Online, May 2020.
  13. 🟦 [HPC Asia'20] Takeo Hosomi, Ryota Yasudo, Michihiro Koibuchi, and Shinji Shimojo, "Dual-Plane Isomorphic Hypercube Network", in Proc. of International Conference on High Performance Computing in Asia Pacific Region, Fukuoka, Japan, January 2020.
  14. 🟪 [CANDAR'19] Masatoshi Hayashikawa, Koji Nakano, Yasuaki Ito, and Ryota Yasudo, "Folded Bloom Filter for High Bandwidth Memory, with GPU implementations", in Proc. of International Symposium on Computing and Networking, Nagasaki, Japan, November 2019.
  15. 🟦 [CANDARW'19] Ryota Yasudo and Koji Nakano, "The Degree/Diameter Problem for Host-Switch Graphs", in Proc. of International Workshop on Parallel and Distributed Algorithms and Applications, in conjunction with CANDAR 2019, Nagasaki, Japan, November 2019.
  16. 🟪 [FPT'18] Ryota Yasudo, Jose Gabriel Figueiredo Continho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, and Tobias Becker, "Performance Estimation for Exascale Reconfigurable Dataflow Platforms", in Proc. of the International Conference on Field-Programmable Technology, Naha, Japan, December 2018.
  17. 🟦 [CANDAR'18] Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, and Hideharu Amano, "k-Optimized Path Routing for High-Throughput Data Center Networks", in Proc. of the Sixth International Symposium on Computing and Networking, Hida Takayama, Japan, November 2018. (Outstanding Paper Award)
  18. 🟪 [FCCM'18] Ryota Yasudo, Ana Lucia Varbanescu, Jose Gabriel Figueiredo Coutinho, Wayne Luk, and Hideharu Amano, "Performance Prediction for Large-scale Heterogeneous Platforms", in Proc. of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, Boulder, CO, United States, April/May 2018.
  19. 🟦 [ICPADS'17] Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, "HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitrary Topologies", in Proc. of the IEEE 23rd International Conference on Parallel and Distributed Systems, pp. 664-673, Shenzhen, China, December 2017. (Acceptance rate: 89/271 = 32.8%)
  20. 🟦 [NOCS'17] Hiroshi Nakahara, Nguyen Anh Vu Doan, Ryota Yasudo, and Hideharu Amano, "XYZ-Randomization using TSVs for Low-Latency Energy-Efficient 3D-NoCs", in Proc. of the 11th International Symposium on Networks-on-Chip (co-located with Embedded Systems Week), Article no. 17, Seoul, South Korea, October 2017. (Acceptance rate: 12/44 = 31.8%)
  21. 🟦 [ICPP'17] Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, and Hideharu Amano, "Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks", in Proc. of the 46th International Conference on Parallel Processing, pp.322-331, Bristol, United Kingdom, August 2017. (Acceptance rate: 60/211 = 28.4%)
    [Paper] [Slides]
  22. 🟦 [I-SPAN'17] Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, and Michihiro Koibuchi, "3D layout of Spidergon, Flattened Butterfly and Dragonfly on a chip stack with inductive coupling through chip interface", in Proc. of the 14th International Symposium on Pervasive Systems, Algorithms, and Networks, IEEE Computer Society Press, pp.52-59, Exeter, Devon, United Kingdom, June 2017.
  23. 🟦 [NOCS'15] Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tadao Nakamura, "On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck", in Proc. of the 9th ACM/IEEE International Symposium on Networks-on-Chip, Article No. 16, pp.1-8, Vancouver, BC, Canada, September 2015. (Acceptance rate: 18/73 = 24.7%)
  24. 🟦 [NOCS'14] Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, and Tadao Nakamura, "Design of a Low Power NoC Router Using Marching Memory Through Type", in Proc. of the 8th IEEE/ACM International Symposium on Networks-on-Chip, pp.111-118, Ferrara, Italy, September 2014. (Acceptance rate: 21/83 = 25.3%)
  25. 🟦 [COOL Chips'14] Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanebe, Tsukasa Oishi, Toru Shimizu, and Tadao Nakamura, "A low power NoC router using the marching memory through type", in Proc. of the17th IEEE Symposium on Low-Power and High-Speed Chips, pp.1-3, Yokohama, Japan, April 2014.
Invited/Keynote Talks
  1. 🟦 [miniCANDAR] Ryota Yasudo, "Graph-theoretic Perspective on Network Topology for Supercomputers", First mini Symposium on Computing and Networking, Tokyo, Japan, June 2019 (keynote).
  2. 🟦 [CANREXI] Ryota Yasudo, "Interconnection Networks with the Optimal Number of Switches and the Optimal Host Distribution", CANDAR Extreme Infrastructure Workshop, Hida Takayama, Japan, December 2018 (invited).
Japanese Journal Paper
  1. 細見岳生, 安戸僚汰, 鯉渕道紘, 下條真司, "二重同型Hypercubeネットワーク", 情報処理学会論文誌, 2021.
Japanese Domestic Conference/Meeting Proceedings
  1. [SWoPP'23] 宮城竜大, 安戸僚汰, 佐野健太郎, 高瀬英希, "ベイジアンネットワーク構造学習のための可塑性を備えたFPGAアクセラレータ", 電子情報通信学会技術研究報告, vol. 123, no.151, RECONF2023-15 (SWoPP'23), 函館, 北海道, 2023年8月.
  2. [SWoPP'23] 織田雅史, 安戸僚汰, 高木直史, "二重対角メッシュメモリネットワークにおけるルーティング手法の検討", 電子情報通信学会技術研究報告, vol. 123, no.145, CPSY2013-16 (SWoPP'23), 函館, 北海道, 2023年8月.
  3. [SWoPP'23] 齊藤一希, 安戸僚汰, 高木直史, "アニーリングマシンによるベイジアンネットワー ク構造学習のビット数削減手法", 電子情報通信学会技術研究報告, vol. 123, no.145, CPSY2013-24 (SWoPP'23), 函館, 北海道, 2023年8月.
  4. [ETNET'23] 飯田智子, 安戸僚汰, 高木直史, "Graph Pointer Networkによる距離行列TSPおよびQAPの高速解法", 電子情報通信学会技術研究報告 (ETNET'23), 徳之島, 鹿児島, 2023年3月.
  5. [ETNET'23] 額見怜央, 安戸僚汰, 高木直史, "深層強化学習を用いた発見的二次無制約二値最適化ソルバーの学習", 電子情報通信学会技術研究報告 (ETNET'23), 徳之島, 鹿児島, 2023年3月.
  6. [ETNET'23] 慶田開, 安戸僚汰, 高木直史, "配線長制限下での平均ホップ数および直径が最小のメモリキューブネットワーク", 電子情報通信学会技術研究報告 (ETNET'23), 徳之島, 鹿児島, 2023年3月.
  7. [ETNET'22] 伊藤光平, 安戸僚汰, 天野英晴, "回線交換マルチFPGAシステムにおけるアプリケーションマッピングツールの実装", 電子情報通信学会技術研究報告 (ETNET'22), オンライン, 2022年3月.
  8. [Design Gaia'18] 河野隆太, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, "高スループットな相互結合網のためのスケーラブルな複数経路選択手法", 電子情報通信学会技術研究報告 (Design Gaia'18), 広島市, 広島, 2018年12月.
  9. [SWoPP'18] 河野隆太, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, "ルーティングアルゴリズムによる通信帯域の測定と理解", 電子情報通信学会技術研究報告, vol. 118, no. 165, CPSY2018-23, pp. 133-138 (SWoPP'18), 熊本市, 熊本, 2018年7月.
  10. [Design Gaia'17] 河野隆太, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, "ターンモデルベースの不規則網向けルーティング", 電子情報通信学会技術研究報告, vol. 117, no. 278, CPSY2017-44, pp. 23-28 / 情報処理学会研究報告, vol. 2017-ARC-228, no. 6, pp. 1-6, (Design Gaia'17), 熊本市, 熊本, 2017年11月.
  11. [COMP研] 安戸僚汰, 鯉渕道紘, 天野英晴, 中野浩嗣, "ホストとスイッチから成る相互結合網の理論モデル", 電子情報通信学会技術研究報告, vol. 116, no. 381, COMP2016-40, pp. 51-58, 東広島市, 広島, 2016年12月.
  12. [SWoPP'16] 安戸僚汰, 藤原一毅, 鯉渕道紘, 松谷宏紀, 天野英晴, 中村維男, "非正則グラフによる低遅延相互結合網の検討", 電子情報通信学会技術研究報告, vol. 116, no. 177, CPSY2016-39, pp. 281-286 / 情報処理学会研究報告, vol. 2016-ARC-221, no. 44, pp. 1-6 (SWoPP'16), 松本市, 長野, 2016年8月.
  13. [1月連合研究会] 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, 中村維男, "分散ルータによる高性能NoC", 電子情報通信学会技術研究報告, vol. 115, no. 399, CPSY2015-127, pp. 149-154 / 情報処理学会研究報告, vol. 2016-ARC-218, no. 26, pp. 1-6, 横浜市, 神奈川, 2016年1月. (情報処理学会 山下記念研究賞 受賞)
  14. [CPSY研究会] 中原浩, 藤木大地, 蓼誠一, 安戸僚汰, 河野隆太, 松谷宏紀, 鯉渕道紘, 中野浩嗣, 天野英晴, "三次元積層チップにおける最大配線長制限下トポロジ最適化", 電子情報通信学会技術研究報告, vol. 115, no. 374, CPSY2015-104, pp. 111-116, 京都市, 京都, 2015年12月.
  15. [SWoPP'15] 中原浩, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, "三次元積層チップへの高性能既存トポロジレイアウト法", 電子情報通信学会技術研究報告, vol. 115, no. 174, CPSY2015-43, pp. 275-280 / 情報処理学会研究報告, vol. 2015-ARC-16, no. 42 (SWoPP'15), pp. 1-6, 別府市, 大分, 2015年8月.
  16. [Design Gaia'14] 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, 中村維男, "トランスペアレントラッチを用いたNoC向け分散ルータアーキテクチャ", 電子情報通信学会技術研究報告, vol. 114, no. 330, CPSY2014-80 (Design Gaia'14), pp. 45-50, 別府市, 大分, 2014年11月.
  17. [Design Gaia'13] 安戸僚汰, 加賀美崇紘, 天野英晴, 中瀬泰伸,渡邊政志, 大石 司, 清水 徹, 中村維男, "マーチングメモリスルータイプを用いたNoCルータ", 電子情報通信学会技術研究報告, vol. 113, no. 324, CPSY2013-71 (Design Gaia'13), pp. 71-76, 鹿児島市, 鹿児島, 2013年11月.
Others
  1. [EMB]安戸僚汰, "並列アニーリング計算の原理と応用:FPGA,ASIC,GPUの事例", 第63回組込みシステム研究発表会, 京都市,京都,2023年7月.(招待有り)
  2. [FIT'22] 安戸僚汰, "大規模な再構成可能データフロー計算基盤の数理的性能推定", 第21回情報科学技術フォーラム(FIT2022), イベント企画「トップカンファレンスセッション6-1 ソフトウェア理解とコンピュータアーキテクチャ」, 横浜市, 神奈川, 2022年9月.(招待有り)
  3. [FIT'21] 安戸僚汰, "複数GPUによる組合せ最適化問題QUBOの新解法アダプティブ・バルク・サーチ", 第20回情報科学技術フォーラム(FIT2021), イベント企画「トップコンファレンスセッション4-1 コンピュータシステム」, オンライン, 2021年8月.(招待有り)
  4. 安戸僚汰, "GPUを駆使した二次無制約二値最適化問題の高速解法", 日本オペレーションズ・リサーチ学会 4部会・グループ合同研究会, オンライン, 2020年10月17日.(招待有り)
  5. [WTCS'19] 安戸僚汰, "Degree/Diameter Problem for Host-Switch Graphs", 第15回 情報科学ワークショップ(WTCS2019), 竹原市, 広島, 2019年9月.
  6. [FIT'19] 安戸僚汰, "ホストスイッチグラフによる高性能相互結合網の設計", 第18回情報科学技術フォーラム(FIT2019), イベント企画「トップコンファレンスセッション7 コンピュータシステム」, 岡山市, 岡山, 2019年9月.(招待有り)
  7. [WTCS'18] 安戸僚汰, "Graph-Theoretic Approach for Designing Low-Latency Interconnection Networks", 第14回 情報科学ワークショップ(WTCS2018), 飯塚市, 福岡, 2018年9月.
  8. [FIT'16] 安戸僚汰, 藤原一毅, 鯉渕道紘, 松谷宏紀, 天野英晴, 中村維男, "可変次数列を持つ相互結合網の構成法", 第15回 情報科学技術フォーラム(FIT2016), 富山市, 富山, 2016年9月.
  9. [FIT'16] 中原浩, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, "高次数規則トポロジの3D-NoCへのレイアウト", 第15回 情報科学技術フォーラム(FIT2016), 富山市, 富山, 2016年9月.
  10. [全国大会] 中原浩, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 中野浩嗣, 天野英晴, "3D-NoCトポロジにおける消費エネルギー・平均最短距離最適化", 情報処理学会 第78回全国大会, 横浜市, 神奈川, 2016年3月.